A time-shared computer system allows each user of the system to interact with the system resources substantially independently of the interactions of other users. Because the cost of system resources is shared among a plurality of users in such a system, each user may be provided with a larger set of resources than would economically be possible to provide to him on a dedicated basis.
A time-shared computer system commonly comprises a plurality of terminals, each dedicated to a user of the system, which are in communication with a central processor that controls the system shared resources and performs computations. Each terminal commonly communicates with the central processor over a separate communication channel, and the plurality of channels are selectively connected to the central processor's single input and output port by a multiplexer. The processor is typically a parallel communicating device whereas the terminals are typically serial communicating devices. Interconnection between the terminals and the processor is provided by input and output interface devices which perform the necessary serial-to-parallel and parallel-to-serial conversions and buffering of communications.
With the continuing improvements in the speed and computing capacity of microelectronics and microcomputers, the potential of computer systems for time-shared use has expanded. However, in prior art systems the interface devices have created a bottleneck between the processor and the terminals, from the standpoint of both economics and performance. Applications of time-shared systems to industrial, business, and educational tasks have not been expanded to their full potential in part because the density of input and output transfers between the processor and the terminals has not been significantly increased without adding to the cost of interface circuitry.
Conventionally, the key element of the interface device has been a Universal Asynchronous Receiver and Transmitter (UART). A separate UART has been provided at the central processor for each channel to enable all terminals to receive and transmit communications simultaneously. Dedication of a UART to each channel at the central processor contravenes the concept of time-sharing, as there is no sharing of the UART capabilities by the system users and hence each channel must bear the full cost of a UART whether or not it is fully utilizing its capabilities. The cost of providing a multiplicity of UARTS can be significant, especially in systems having many terminals.
To alleviate this economic disadvantage, the prior art has allowed some sharing of interface circuitry between the channels at the central processor. However, current modules of this type still require substantial circuitry dedicated to each channel in addition to the shared circuitry. And the dedicated circuitry is often more complex and more closely than a UART which performs all required channel functions with no sharing of circuitry. Furthermore, the shared interfaces of the prior art have not interfaced the communications of all associated channels simultaneously. Rather they have serviced the channels sequentially, one at a time, while forcing the channels not currently being serviced to wait for service. The performance capability of the shared interfaces has been lacking as a result.